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R8A66162SP
32-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
REJ03F0263-0100 Rev. 1.00 Jan. 24. 2008
DESCRIPTION
The R8A66162SP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel output shift register, equipped with direct set input and output latches. The R8A66162SP guarantees sufficient 24mA (Vcc=5.0V case) output current to drive anode common LED, allowing 32-bit simultaneous and continuous current output. The parallel outputs are open-drain outputs. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. R8A66162SP is the succession product of M66313FP.
FEATURES
Anode common LED drive VCC 5V or 3.3V single power supply High output current: All parallel outputs Q1~Q32 IOL=24mA (at VCC=5.0V), IOL=12mA (at VCC=3.3V), LEDs can be turned on simultaneously. Low power dissipation: 200uW/package (max) (VCC=5.0V, Ta=25OC, quiescent state) High noise margin: Employment of Schmitt-trigger circuit on all inputs allows application with long wiring. Direct set input (SD) Open-drain output (Q1~Q32) Serial data output for cascading (SQ32) Wide operating temperature range (Ta=-40oC~+85oC) Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED connection)
APPLICATION
LED array drive, The various LED display modules PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipments
BLOCK DIAGRAM
LOGIC DIAGRAM
Q1
2 PARALLEL DATA OUTPUTS SERIAL DATA OUTPUT
Q2
3
Q3
4
Q4
5
Q29 Q30 Q31 Q32
20 21 22 23
SQ32
17
Vcc
9 15 37
0 LE DS
0 LE DS
0 LE DS
0 LE DS
0 LE DS
0 LE DS
0 LE DS
0 LE DS
1 CK DS
1 CK DS
1 CK DS
1 CK DS
1 CK DS
1 CK DS
1 CK DS
1 CK DS
S
S
S
S
S
1
8 16 24
11
10
14
DATA SIGNAL OE SIGNAL PARALLEL DATA OUTPUTS SERIAL DATA OUTPUT
13
12
30 36 43
OE
A
CK
SD
LE
GND
OUTPUT SERIAL ENABLE DATA INPUT INPUT
Q1
Q32
SQ32
SHIFT DIRECT LATCH CLOCK SET ENABLE INPUT INPUT INPUT
OUTPUT FORMAT
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 1 of 7
R8A66162SP
PIN CONFIGURATION ( TOP VIEW )
GND Q1 Q2 Q3 Q4 Q5 Q6 GND VCC A OE LE SD CK VCC GND SQ32 Q27 Q28 Q29 Q30 Q31 Q32 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PARALLEL DATA OUTPUTS
SERIAL DATA INPUT OUTPUT ENABLE INPUT LATCH ENABLE INPUT DIRECT SET INPUT SHIFT CLOCK INPUT
SERIAL DATA OUTPUT
PARALLEL DATA OUTPUTS
Q7 Q8 Q9 Q10 Q11 GND Q12 Q13 Q14 Q15 Q16 VCC GND Q17 Q18 Q19 Q20 Q21 GND Q22 Q23 Q24 Q25 Q26
PARALLEL DATA OUTPUTS
PARALLEL DATA OUTPUTS
PARALLEL DATA OUTPUTS
PARALLEL DATA OUTPUTS
FUNCTIONAL DESCRIPTION
The employment of silicon gate CMOS process of the R8A66162SP guarantees low power dissipation and maintains high noise margin as well as high output current and high speed required to drive LEDs. Each shift register bit consists of a flip-flop for shifting and an output latch. The shift operation takes place when the shift clock input CK changes from low-level to high-level. The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is shifted in sequence when a pulse is applied to CK. If the latch-enable input LE is turned high-level, the content of the shift register at that instant is latched. The parallel data outputs Q1~Q32 are open-drain outputs. To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of the 32nd bit. If the direct set input SD is turned low-level, Q1~Q32 and SQ32 are set. Then shift register and latches are set. If the high-level input is applied to the output enable input OE, Q1~Q32 are set to the high-impedance state, but SQ32 is not set to the high-impedance state. The shift operation is not affected when OE is changed.
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 2 of 7
R8A66162SP
FUNCTION TABLE (Note: 1)
SERIAL OUTPUT
OPERATION MODE
INPUT
SD CK LE A OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
PARALLEL OUTPU TS
Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32
SQ32
SET
L H
X
X L L
X H L X
L L L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
2 L Q 01 Q 0 Q03 Q04 Q05 Q06 Q 07 Q08 Q 09 Q 010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q 020 Q 021 Q022 Q023 Q024 Q025 Q 026 Q027 Q028 Q 029 Q 030 Q031 q 031
SHIFT H LATCH H X Z Q 01 Q02 Q 03 Q04 Q 05 Q06 Q07 Q08 Q09 Q 010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q 020 Q 021 Q022 Q023 Q024 Q025 Q 026 Q027 Q028 Q 029 Q 030 Q031 q0 31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32
H
L Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 Q 10 Q 11 Q 12 Q 13 Q 14 Q 15 Q 16 Q 17 Q 18 Q 19 Q 20 Q 21 Q 22 Q 23 Q 24 Q 25 Q 26 Q 27 Q 28 Q 29 Q 30 Q 31 Q 32 q
q
OUTPUT DISX ABLE
X
X
X
HZ
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
32
Note 1.
Q X q0 q Z
0
Transition from low-to-high-level Sho the status of output Q before CK input changes ws Irrelevant The content of shif t register before CK changes The content of shif t register High-impedance state
ABSOLUTE MAXIMUM RATINGS (Ta=-40~85 C, unless otherwise noted)
Symbol Vcc VI VO IO Icc Pd Parameter Supply voltage Input voltage Output voltage Output current per output pin Supply/GND current Power dissipation Storage temperature range Conditions Ratings -0.5~+7.0 -0.5~Vcc+0.5 -0.5~Vcc+0.5 50 25 -920, +20 650 -65~150 Unit V V V mA mA mW
o
o
Q1~Q32 SQ32 Vcc, GND
Tstg
C
RECOMMENDED OPERATING CONDITIONS (Ta=-40~85 C, unless otherwise noted)
Symbol
o
Parameter Supply voltage Input voltage Output voltage Operating temperature range 5.0V support 3.3V support Min. 4.5 3.0 0 0 -40
Vcc VI VO Topr
Limits Typ. 5.0 3.3
Unit Max. 5.5 3.6 Vcc Vcc 85 V V V V
o
C
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 3 of 7
R8A66162SP
ELECTRICAL CHARACTERISTICS 5.0V version support specifications (Ta=-40~85 C, Vcc=4.5V~5.5V, unless otherwise noted)
o
Symbol VT+ VTVOH VOL
Parameter Positive going threshold voltage Negative going threshold voltage High level SQ32 output voltage Low level Q1~Q32 output voltage SQ32
Test conditions Min. 0.35xVcc 0.20xVcc VI=VT+, VTVcc=4.5V VI=VT+, VTVcc=4.5V IOH=-20uA IOH=-4mA IOL=20uA IOL=24mA IOL=28mA IOL=20uA IOL=4mA Vcc=5.5V Vcc=5.5V VO=Vcc VO=GND Vcc-0.1 3.66
Limits Typ.
Unit Max. 0.70xVcc 0.55xVcc V V V 0.10 0.50 0.55(Note2) 0.10 0.53 5 -5 10 -10 400 V
IIH IIL IO
High level input current Low level input current Maximum Q1~Q32 output leakage current Quiescent supply current
VI=Vcc VI=GND VI=VT+, VTVcc=5.5V
uA uA uA
Icc
VI=Vcc, GND Vcc=5.5V
uA
Note2 : Ta = -40~70oC
3.3V version support specifications (Ta=-40~85 C, Vcc=3.0V~3.6V, unless otherwise noted)
o
Symbol VT+ VTVOH VOL
Parameter Positive going threshold voltage Negative going threshold voltage High level SQ32 output voltage Low level Q1~Q32 output voltage SQ32 High level input current Low level input current Maximum Q1~Q32 output leakage current Quiescent supply current
Test conditions Min. 0.35xVcc 0.20xVcc VI=VT+, VTVcc=3.0V VI=VT+, VTVcc=3.0V IOH=-20uA IOH=-2mA IOL=20uA IOL=12mA IOL=20uA IOL=2mA Vcc=3.6V Vcc=3.6V VO=Vcc VO=GND Vcc-0.1 2.60
Limits Typ.
Unit Max. 0.70xVcc 0.55xVcc V V V 0.10 0.54 0.10 0.40 5 -5 10 -10 400 V
IIH IIL IO
VI=Vcc VI=GND VI=VT+, VTVcc=3.6V
uA uA uA
Icc
VI=Vcc, GND Vcc=3.6V
uA
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 4 of 7
R8A66162SP
o
SWITCHING CHARACTERISTICS (Ta=-40~85 C, Vcc=5.0V or 3.3V, unless otherwise noted)
Symbol
Parameter Maximum clock frequency CK-Q1~Q32 Output "Z-L" and "L-Z" (Turned on) propagation time CK-Q1~Q32 (Turned off) Output "L-H" and "H-L" CK-SQ32 propagation time Output "Z-L" SD-Q1~Q32 propagation time (Turned on) Output "L-H" SD-SQ32 propagation time LE-Q1~Q32 Output "Z-L" and "L-Z" (Turned on) propagation time LE-Q1~Q32 (Turned off) Output "Z-L" and "L-Z" OE-Q1~Q32 propagation time (Turned on) OE-Q1~Q32 (Turned off) Input capacitance Output capacitance
Test conditions
fmax tPZL tPLZ tPLH tPHL tPZL tPLH tPZL tPLZ tPZL tPLZ CI CO
5.0V specification Min. Typ. Max. 4 200 250 125 125 200 125 125 200 125 200 10 15
3.3V specification Min. Typ. Max. 3.3 220 270 150 150 220 150 150 220 150 220 10 15
Unit MHz ns ns ns ns ns ns ns ns ns ns pF pF
CL=50pF RL=1k (Note3)
OE=Vcc
TIMING REQUIREMENTS (Ta=-40~85 C, Vcc=5.0V or 3.3V, unless otherwise noted)
Symbol tw tsu th trec Parameter CK, LE, SD pulse width Setup time A to CK Hold time A to CK Hold time LE to CK Recovery time CK to SD Test conditions 5.0V specification Min. Typ. Max. 125 125 15 70 70 3.3V specification Min. Typ. Max. 150 150 20 80 80 Unit ns ns ns ns ns
o
(Note3)
Note3.
Test circuit
INPUT VCC
VCC RL
PG 50
DUT SQ32 GND CL CL
Q1
Q32
(1) The pulse generator(PG) has the following characteristics(10%~90%):tr=6ns,tf=6ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 5 of 7
R8A66162SP
TIMING DIAGRAM
tw tw tw
VCC CK
50% tPLH 50% 50%
VCC LE
50% tPZL 50%
GND
tPHL
GND VCC
SQ32
VOH
50% tPLZ 50%
VOL
tPZL
Q1
Q32
50%
VOL
tPLZ
Q1
Q32
VCC
10% 50%
VOL
Q1
Q32
VCC
10%
VOL
tw
VCC SD
50% 50% trec
VCC A
50% tsu th 50%
GND VCC CK GND VOH
GND VCC
50%
CK
tPLH
50%
GND
SQ32
50%
VOL
tPZL 50%
VCC VOL
Q1
Q32
th
VCC OE
50% tPZL 50%
VCC
50%
LE
GND
tPLZ
GND CK VCC
50%
Q1
Q32
50%
VCC
10%
VOL Q1 Q32
GND VCC VOL
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 6 of 7
R8A66162SP
PACKAGE OUTLINE
Package 48pin SSOP RENESAS Code PRSP0048ZB-A Previous Code 48P2X-A
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 7 of 7

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